Field of Technology
The present invention relates to a liquid crystal display (LCD) device and a method of manufacturing the same, and more particularly, to a LCD device having a dual link structure which includes a plurality of link lines disposed at dense intervals on a first layer and a second layer different from the first layer. The present invention provides an LCD device having a dual link structure, and particularly, provides a method of manufacturing an LCD device which proposes a new manufacturing process for reducing the number of masks used in a manufacturing process and can easily manufacture the LCD device in consideration of the possibility of misalignment of exposure equipment.
Discussion of the Related Art
FIG. 1 is a plan view illustrating an array substrate in which a plurality of switching elements are provided, in a general LCD device. In the LCD device, two substrates with electrodes formed therein face each other and are adhered to each other by a sealant, and liquid crystal is injected therebetween. The liquid crystal is a material having light transmittance anisotropy, and changes a phase of light according to a direction in which the light passes through the liquid crystal. The operation principle of LCD devices is that a polarizer, which changes a phase of light and transmits only specific directional light, transmits and blocks light to realize an image. Also, an alignment direction of the liquid crystal is adjusted by selectively applying voltages to the electrodes formed on the two substrates, in which case the liquid crystal is driven with electric fields generated by the voltages applied to the electrodes and thus the alignment direction of the liquid crystal is changed.
A panel, which is configured with the two coupled substrates and the liquid crystal injected therebetween, is called a LCD panel.
A process of manufacturing the LCD panel includes: a process of manufacturing an array substrate in which a plurality of pixel electrodes (first electrodes) for applying an electric field to the liquid crystal and a plurality of thin film transistor (TFTs, switching elements) for selectively supplying a voltage to a corresponding pixel electrode are provided; a process of manufacturing a color filter substrate, facing the array substrate, in which a plurality of common electrodes (second electrodes) for applying the electric field to the liquid crystal and a plurality of red (R), green (G), and blue (B) color filters are provided; and a process of injecting the liquid crystal between the two substrates.
FIG. 1 schematically illustrates a plan view of an array substrate. FIG. 2 is an enlarged sectional view of an area A illustrated in FIG. 1.
Referring to FIG. 1, an array substrate 1 is divided into an active area AA, in which a plurality of unit pixels are arranged, and an inactive area NA disposed outside the active area AA.
In the active area, a plurality of gate lines GL are laterally arranged, and a plurality of data lines DL are vertically arranged to perpendicularly intersect the gate lines GL.
One area defined by the gate line GL and the data line DL is a unit pixel area C. An area C of FIG. 1 illustrates the enlarged unit pixel area C.
In the one unit pixel area, one pixel electrode P for applying an electric field to liquid crystal is provided, and a thin film transistor (switching element) Tr for selectively applying a voltage to the pixel electrode P is provided at a corner portion of the unit pixel area.
The thin film transistor Tr includes a gate electrode connected to a corresponding gate line GL, a source electrode connected to a corresponding data line DL, a drain electrode facing the source electrode, and an active layer that is a semiconductor layer formed of amorphous silicon or polycrystalline silicon.
In the thin film transistor Tr, when a scan signal is applied from the gate line to the gate electrode, a channel of the active layer is opened by the scan signal, and simultaneously, when a pixel signal is applied from the data line, the pixel signal is transferred to the drain electrode through the source electrode and the active layer. Since the drain electrode is connected to the pixel electrode, the pixel signal is applied to the pixel electrode.
A driving circuit unit (D-IC) for supplying signals to the gate lines GL and data lines DL disposed in the active area AA is disposed in the inactive area NA. The driving circuit unit is generally divided into a gate driving circuit unit and a data driving circuit unit, but, one driving circuit unit for supplying both a gate signal and a data signal may be used as shown in FIG. 1. FIG. 1 illustrates one driving circuit unit supplying both a gate signal and a data signal.
Moreover, a plurality of link lines are further disposed in the inactive area NA. The link lines are divided into a plurality of gate link lines GLL that connect the gate lines GL to the driving circuit unit (D-IC) and a plurality of data link lines DLL that connect the data lines DL to the driving circuit unit (D-IC).
Referring to FIG. 1, the area A illustrates the gate link lines, and an area B illustrates the data link lines.
The gate link lines GLL are disposed on a first layer with the gate lines GL disposed therein, and the data link lines DLL are disposed on a second layer with the data lines DL disposed therein.
The gate link lines GLL are respectively connected to the gate lines GL, and the data link lines DLL are respectively connected to the data lines DL.
Moreover, a seal pattern S that couples the array substrate 1 to the color filter substrate (not shown) facing the array substrate 1 is further disposed in the inactive area NA.
The seal pattern S passes over the gate link lines GLL and the data link lines DLL and is disposed in a closed loop type in the inactive area. The seal pattern S is generally formed of a photosensitive organic material having adhesiveness.
FIG. 2 is an enlarged sectional view of the area A illustrated in FIG. 1. Referring to FIG. 2, the plurality of gate link lines GLL are disposed on a first substrate 11. Although not shown, the plurality of gate lines GL are disposed on the first substrate 11. Thus, a gate line and a gate link line GLL are formed of the same material, on the same layer.
A plurality of the gate link lines GLL are covered and insulated by a gate insulating layer 12, and a passivation layer (insulating layer) 13 is further formed on the gate insulating layer 12. Although not shown in FIG. 2, each of a data line and a data link line are formed in plurality on the gate insulating layer 12. The seal pattern S that couples a color filter substrate (upper substrate) 2 to an array substrate (lower substrate) is formed over the gate link lines GLL to couple the two substrates.
Like this, the gate link lines GLL and the data link lines DLL are formed on the same layer as their respective gate lines GL and data lines DL, namely, the gate link lines GLL are formed on the first substrate 11 and the data link lines DLL are formed on the gate insulating layer 12. However, in recent LCD devices, a bezel tends to narrow, and thus, the area of the inactive area is continuously reduced. On the other hand, resolutions of the LCD devices increase continuously, causing an increase in the numbers of gate link lines of data link lines disposed in a unit area.
Moreover, in manufacturing an LCD device, a need for reducing the number of masks to increase productivity is continuously increasing. That is, in manufacturing a thin film transistor, since the number of masks used to manufacture the LCD device has a close relationship with the cost and a yield rate, development of a process for reducing the number of masks is a very important production factor.